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ADE7854/ADE7858/ADE7868/ADE7878
THEORY OF OPERATION
ANALOG INPUTS
The ADE7868 / ADE7878 have seven analog inputs forming
current and voltage channels. The ADE7854 / ADE7858 have six
Data Sheet
Figure 29 shows how the gain selection from the gain register
works in both current and voltage channels.
GAIN
SELECTION
analog inputs, not offering the neutral current. The current
channels consist of four pairs of fully differential voltage inputs:
IAP and IAN, IBP and IBN, ICP and ICN, and INP and INN.
These vol-tage input pairs have a maximum differential signal of
IxP, VyP
IxN, VN
V IN
K × V IN
V CM = ±25mV MAX
±0.5 V. In addition, the maximum signal level on analog inputs
for the IxP/IxN pair is ±0.5 V with respect to AGND. The
maximum common-mode signal allowed on the inputs is ±25 mV.
Figure 27 presents a schematic of the input for the current
channels and their relation to the maximum common-mode
voltage.
DIFFERENTIAL INPUT
V 1 + V 2 = 500mV MAX PEAK
COMMON MODE
V 1 + V 2
NOTES
1. x = A, B, C, N
y = A, B, C.
Figure 29. PGA in Current and Voltage Channels
ANALOG-TO-DIGITAL CONVERSION
The ADE7868 / ADE7878 have seven sigma-delta (Σ-Δ) analog-
to-digital converters (ADCs), and the ADE7854 / ADE7858 have
six Σ-Δ ADCs. In PSM0 mode, all ADCs are active. In PSM1
mode, only the ADCs that measure the Phase A, Phase B, and
+500mV
V 1
IAP, IBP,
ICP, OR INP
Phase C currents are active. The ADCs that measure the neutral
current and the A, B, and C phase voltages are turned off. In
V CM
–500mV
V CM
V 2
IAN, IBN,
ICN, OR INN
PSM2 and PSM3 modes, the ADCs are powered down to
minimize power consumption.
For simplicity, the block diagram in Figure 30 shows a first-
LOW-PASS FILTER
FILTER
COMPARATOR
V CM = ±25mV MAX
Figure 27. Maximum Input Level, Current Channels, Gain = 1
All inputs have a programmable gain amplifier (PGA) with a
possible gain selection of 1, 2, 4, 8, or 16. The gain of IA, IB, and
IC inputs is set in Bits[2:0] (PGA1[2:0]) of the gain register. For
the ADE7868 and ADE7878 only, the gain of the IN input is set
in Bits[5:3] (PGA2[2:0]) of the gain register; thus, a different gain
from the IA, IB, or IC inputs is possible. See Table 44 for details
on the gain register.
The voltage channel has three single-ended voltage inputs: VAP,
VBP, and VCP. These single-ended voltage inputs have a maximum
input voltage of ±0.5 V with respect to VN. In addition, the max-
imum signal level on analog inputs for VxP and VN is ±0.5 V
with respect to AGND. The maximum common-mode signal
allowed on the inputs is ±25 mV. Figure 28 presents a schematic
of the voltage channels inputs and their relation to the maximum
common-mode voltage.
DIFFERENTIAL INPUT
V 1 + V 2 = 500mV MAX PEAK
COMMON MODE
V 1
order Σ-Δ ADC. The converter is composed of the Σ-Δ modulator
and the digital low-pass filter.
CLKIN/16
ANALOG
DIGITAL
INTEGRATOR LOW-PASS
LATCHED
R +
+
–
C – 24
V REF
.....10100101.....
1-BIT DAC
Figure 30. First-Order Σ -? ADC
A Σ-Δ modulator converts the input signal into a continuous
serial stream of 1s and 0s at a rate determined by the sampling
clock. In the ADE7854 / ADE7858 / ADE7868 / ADE7878 , the
sampling clock is equal to 1.024 MHz (CLKIN/16). The 1-bit
DAC in the feedback loop is driven by the serial data stream.
The DAC output is subtracted from the input signal. If the loop
gain is high enough, the average value of the DAC output (and,
therefore, the bit stream) can approach that of the input signal
+500mV
V CM
–500mV
V 1
V CM
VAP, VBP,
OR VCP
VN
level. For any given input value in a single sampling interval, the
data from the 1-bit ADC is virtually meaningless. Only when a
large number of samples are averaged is a meaningful result
obtained. This averaging is carried out in the second part of the
ADC, the digital low-pass filter. By averaging a large number of
Figure 28. Maximum Input Level, Voltage Channels, Gain = 1
All inputs have a programmable gain with a possible gain
selection of 1, 2, 4, 8, or 16. To set the gain, use Bits[8:6]
(PGA3[2:0]) in the gain register (see Table 44).
bits from the modulator, the low-pass filter can produce 24-bit
data-words that are proportional to the input signal level.
The Σ-Δ converter uses two techniques to achieve high resolu-
tion from what is essentially a 1-bit conversion technique. The
first is oversampling. Oversampling means that the signal is
sampled at a rate (frequency) that is many times higher than
Rev. H | Page 28 of 100
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